Referring to FIG. 1, a block diagram of a conventional digital camera 20 is shown. A sensor 22 converts optical pictures into electronic pictures. A digital signal processor (DSP) 24 of the camera 20 includes an image processing circuit 26 that processes the electronic pictures into an intended format, a final size and a specified quality. A memory 28 (i.e., digital random access memory (DRAM)) is in communication with the DSP 24 to buffer processed image data created by the image processing circuit 26. A compression circuit 30 compresses and encodes the image data into a standard storage or transmission format, such as JPEG (Joint Photographic Experts Group), MPEG-2 (Motion Picture Expert Group) or H.264/AVC (“Advanced Video Coding” specification). The compressed data is buffered in the memory 28. A driver circuit 32 reads the compressed data from the memory 28 and conveys the compressed data to a storage media or a transmission media.
During operations, the digital camera 20 reads and writes large amounts of image data to and from the memory 28. Transfers of the image data can significantly increase a power consumption and a cost of the digital camera 20 since more expensive or more external memory 28 chips are used to accommodate the increased bandwidth. Moreover, space must be allocated within the memory 28 for the image data resulting in large or expensive DRAMS.
As such, having a method to reduce the power and cost associated with storing and reading large amounts of image data to and from an external DRAM is desirable.